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Synchronizing two USB-1608FS A/D devices, using the same internal...

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Synchronizing two USB-1608FS A/D devices, using the same internal clock


There are several approaches to synchronizing the AI sampling of two USB-1608FS units (this article also applies to the USB-1616FS and USB-1608FS-PLUS models).  Below I list three approaches, but I will discuss in detail only the third:

1) Use each unit's own internal clock, but start the sampling with a common external digital start trigger.   This is a reasonable approach, but without using a common clock, the sampling across units can be skewed slightly over time.

2) Clock both units with a common external clock.  This insures there is no clock skew, but care must be taken to insure both units start on the very same clock pulse (either inhibit the external clock until both units are configured in software for scanning, or also use a common external digital start trigger).

3) Use one unit to drive the clock input on the other.  This approach is accommodated in the design of the USB-1608FS, and does not require any external timing signals.  This is the only approach covered in this article.

The USB-1608FS model has a SYNC pin.   This pin is bi-directional and it carries the clock signal.  The default direction is input (the direction is set manually in InstaCal) .  If you wish to have two units sample in a synchronized fashion, based on the internal clock of just one of them, then below is the strategy:

A) Connect both USB-1608FS boards to the PC, and run InstaCal to have them both recognized.  One becomes logical board # 0, and one becomes logical board # 1.  

B) In InstaCal, enable the SYNC pin to the output direction on board # 0.   Thus we plan to use board # 0 to be the master.  The clock from the master will drive the slave board (board # 1).

C) Connect a physical wire between the SYNC pins of both boards.

D) In your software program, configure both AInScans to be for the same # of samples per channel.  In this way, the correct number of clock pulses will travel down the SYNC wire.  

E) First start a BACKGROUND A/D scan on the slave board (board # 1), and specify that it use EXTCLOCK (external clock).  Choose background since we need the program control to continue (a foreground scan will halt the program flow unit all data is collected, not allowing us to start the other scan).  Note that since no clock pulses have arrived from the master to the slave, the scan on the slave can be considered armed, but no A/D conversions have occurred yet.

F) Next start the A/D scan on the master board (board # 0).  The result will be that clock pulses from the master will not only clock its own A/Ds, but will travel down the wire and clock the slave's A/Ds.

G) Proceed to manage the data flow for both scans.  This is done in the same manner as you would for one scan, except you do it "independently" for each scan.  Note that from the software driver's standpoint, the data is coming from two devices, into two different memory buffers.  



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Article ID: 50419

Last Modified:12/17/2012 8:12:08 AM

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